Highlights:

  • The Core Ultra 9 285K is the flagship chip in the Core Ultra 200S series. It has eight cores with a maximum frequency of 5.6 gigahertz that are tuned for performance.
  • Intel has improved the branch prediction mechanism of the cores, which expedites processing by performing some calculations earlier than necessary.

Intel Corp. launches Core Ultra 200S, a new desktop processor series featuring five chips developed with 3D packaging technology.

In comparison to previous-generation silicon, the business promises a single-threaded performance gain of up to nine percent. A 14% speed gain is available with the Core Ultra 200S for multithreaded workloads. Depending on the workload, power consumption can be as much as 58% less.

The Core Ultra 9 285K is the flagship chip in the Core Ultra 200S series. It has eight cores with a maximum frequency of 5.6 gigahertz that are tuned for performance. Additionally, there are sixteen efficiency-optimized cores that consume significantly less power despite having a lower top speed of 4.6 gigahertz.

There are 12 to 20 cores in each of the other four Core Ultra 200S series CPUs. All of them are built on the same architecture as the flagship Core Ultra 9 285K.

The performance-optimized cores of the chips are built on an architecture known by Intel as Lion Cove. Due to an enhanced cache, it runs 9% faster than the company’s previous-generation design. Additionally, Intel has improved the branch prediction mechanism of the cores, which expedites processing by performing some calculations earlier than necessary.

The efficiency-optimized cores in the Core Ultra 200S series result in greater performance gains. Intel claims that their silicon can calculate floating point values up to 72% faster than that of earlier generations. Integer-based tasks are also accomplished more quickly.

A chiplet known by Intel as the computing tile houses the cores of a Core Ultra 200S CPU. It is based on the N3B method developed by Taiwan Semiconductor Manufacturing Co. Ltd. This is a modified version of TSMC’s three-nanometer node, which reduces production costs by utilizing severe ultraviolet lithography equipment less frequently.

The computational tile is integrated with multiple additional chiplets produced by TSMC. An Intel-claimed graphics processing unit found in one chiplet can process images up to twice as quickly as its preceding acceleration. While circuitry in another module controls the data flow into and out of the processor, a so-called SoC tile houses several auxiliary parts.

The foundation tile is the layer upon which all those modules are positioned. They are connected via a packaging innovation known as Foveros, which enables chiplets to be stacked on top of one another in a three-dimensional arrangement.

Foveros transfers power and data between processor chiplets using minuscule metal parts known as microbumps. Because the microbumps are spaced only a few dozen micrometers apart, a chip’s square millimeter can contain up to 770 of them. Up to 160 gigabytes of data per second can be moved up and down a processor’s vertically stacked chiplets by each square millimeter patch of microbumps.

Vice President and General Manager of AI and technical marketing at Intel’s client computing group, Robert Hallock, said, “The new Intel Core Ultra 200S series processors deliver on our goals to significantly cut power usage while retaining outstanding gaming performance and delivering leadership compute. The result is a cooler and quieter user experience.”

Later this month, the Intel Core Ultra 200S series is expected to be released. Overclocking software, which enables users to raise the cores’ clock frequency over the factory-set maximum, will be included with the chips when they are shipped. Other parts, like the connection that joins the chiplets of a Core Ultra 200S CPU, can also have their speeds increased.