Highlights:

  • According to a report from The Information, which cites three unnamed sources, the project has been codenamed “Baltra” and is expected to launch in 2026.
  • Broadcom’s 3.5D XDSiP is a blueprint for building multi-die processors, similar to AMD’s MI300X GPUs.

 

Apple Inc. is collaborating with Broadcom Inc. to develop a custom server processor designed to enhance the artificial intelligence capabilities of the iPhone maker’s iOS operating system.

According to a report from The Information, which cites three unnamed sources, the project has been codenamed “Baltra” and is scheduled for launch in 2026.

The report reveals few additional details, which is unsurprising given the secretive nature of both companies. However, during Apple’s developer conference earlier this year, Craig Federighi, Apple’s senior vice president of software engineering, mentioned that some Apple Intelligence features will rely on on-device chips, while others will operate on cloud-based servers powered by the company’s proprietary chips.

If Apple is indeed creating its own chips for generative AI, it wouldn’t be unexpected. The company has been utilizing its own Arm-based central processing units for years. Similarly, Broadcom’s involvement in such a project isn’t surprising, as the company already collaborates with Apple on components like 5G modems.

The reason behind Apple seeking Broadcom’s expertise once again remains unclear, but one possibility is its interest in Broadcom’s semiconductor interconnect designs, which enable faster chip-to-chip communication. Earlier this year, Broadcom introduced a new optical interconnect chiplet designed for use with graphics processing units and other AI accelerators, along with its 3.5D packaging technology, which facilitates scaling chips beyond current limitations.

Broadcom’s 3.5D eXtreme Dimension System in Package (3.5D XDSiP) serves as a framework for building multi-die processors, similar to the MI300X GPUs from Advanced Micro Devices Inc. These chips integrate eight compute chiplets stacked vertically on top of four input/output dies, which manage chip-to-chip communication and memory operations.

Instead of stacking chips vertically, Broadcom’s design reportedly employs a face-to-face configuration, allowing for denser electrical interfaces between chiplets using hybrid copper bonding (HBC) technology. According to Broadcom, this approach enables significantly faster die-to-die interconnect speeds and shorter signal paths, resulting in much higher bandwidth for communication between chips.

Broadcom stated that its largest 3.5D XDSiP designs can accommodate two 3D stacks, two I/O chiplets, and up to 12 high-bandwidth memory (HBM) modules within a single package. The company plans to begin production of the 3.5D XDSiP packaging technology in 2026.

With Apple’s Baltra project following a similar timeline, it’s plausible that the company’s custom server processor could leverage the same technology, though this remains unconfirmed. There is precedent for this, as some of Apple’s chips, like the M2 Ultra, already utilize multi-die architectures.

For now, this remains speculative, and we likely won’t learn more about Baltra until its official announcement, which is probably not until 2026. This is due to Apple’s well-known secrecy about its upcoming projects, while Broadcom is equally secretive about who is using its technology.